Advanced Solutions for LVF .lib Sign-off Verification using ML [whitepaper]
On-chip variation (OCV) is a significant factor affecting timing sign-off for digital designs at 20nm and below. At 7nm, timing measurements such as propagation delay, setup time, and hold time may change by 50%-100% due to statistical variation. In order to capture these variation effects accurately, timing .libs for 20nm and smaller process nodes include variation modeling information defined by the Liberty® Variation Format (LVF).
LVF requires that each timing data point must also perform a Monte Carlo analysis in order to capture the full distribution of behavior. Since each brute-force Monte Carlo analysis requires thousands of additional simulations (across all timing measurements defined in the .libs), characterization tools use various methods to make runtime feasible. These methods introduce approximations and inaccuracies that may invalidate library timing data, resulting in chip tapeout delays or silicon failure. Therefore, verifying LVF data is a critical step for chip tapeout success.
Solido provides a sign-off solution for verifying LVF data in .libs using advanced Machine Learning (ML)-enabled technology. Using Solido’s Analytics and Variation Designer tools results in a workflow that correctly and automatically identifies all LVF problem areas, and accurately re-simulates any points that do not meet production targets. The end result is sign-off verified LVF .libs that can be confidently used in production.
