Custom IC Design Solution

Plotting small-signal parameters

This article describes how to plot small-signal parameters of a component in your design. We will show how to configure the plotting settings both from the GUI as well as by netlisting to achieve this purpose.

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Pin placement methods for Tanner Digital Implementer

The pin placement of your design's floorplan generated from P&R can be customised in two methods: By drawing the floorplan and drawing the pins in L-Edit; and by customising your P&R scripts to source pin locations and insert them during P&R. This article describes these two methods in detail.

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Performing XOR using Calibre One

Calibre provides XOR through the DRC verification option to compare two layout cells in Tanner tools. There are two layout comparison flows through the Calibre DRC integration, FastXOR and XOR. This technote will go over the Layout vs Layout techniques when running not using FASTXOR.

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Creating multiple simultaneous cell windows

When working with multiple windows, a user may want to stack or create dockable views of cells to manage screen space efficiently and simultaneously access multiple views. This feature is available in S-Edit and L-Edit through the same methods.

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Netlisting in S-Edit via Tcl Procedures

S-Edit allows running netlisting procedures in Tcl that would enable greater control over how your device or subcircuit can be netlisted. This guide will explain how to create a Tcl netlister for your devices, supported by examples.

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