The Aprisa place-and-route platform is a detail-route-centric solution to the challenges of modern digital IC implementation.
Designing at advanced process nodes requires a new place-and-route paradigm to manage the increasing complexity. Aprisa is a detail-route-centric physical design platform for the modern SoC.
Challenges in Digital Implementation
Managing design complexity, performance/power/area targets, and time-to-market are crucial challenges in modern SoC design. Design rule complexity and meeting timing make design closure more challenging than ever, and calls for a paradigm shift in place-and-route.
Achieving DRC Closure
Extensive use of multiple-patterning technology, EUV lithography and mixed-height cells complicates placement and routing. Fundamental changes to place-and-route technology are required to effectively achieve DRC closure.
Delivering Competitive PPA
The market wants ICs with the lowest power use and highest performance. Break-through optimization technologies can minimize power while achieving timing and area targets and controlling development cost.
Reducing Time-to-Closure
Accurate post-route timing estimation is harder than ever with the increase in wire/via resistance. Avoid iterations, improve PPA, and reduce time-to-closure by pulling detail route visibility earlier in the flow.
Accelerate SoC design with place-and-route technology
Aprisa digital implementation is an RTL2GDSII solution that offers complete synthesis and place-and-route functionality for top-level hierarchical designs and block-level implementation. It’s tapeout quality correlation with signoff tools, both for STA timing and DRC, reduces design closure and ensures optimal power, performance and area (PPA).
Benefits of using Aprisa SoC design software?
Aprisa delivers optimal PPA out-of-the-box. This helps physical designers reduce the effort at each step of the place-and-route flow and achieve faster time-to-market
Fast design closure
Unified architecture and common analysis engines ensure excellent timing and DRC correlation between implementation steps and with signoff tools, greatly reducing the number of flow iterations and ECOs
Unmatched out-of-the-box PPA
Aprisa’s detail-route-centric architecture delivers excellent out-of-the-box results through reference flows that eliminate the need for place groups or margins during placement and CTS
AI technologies to aid designers on tasks
AI-driven Auto Macro Placement (AMP) technology delivers expert designer quality macro placement at a fraction of the time
Best cost-of-ownership
Certified at the most advanced nodes by the main Foundries,
while supporting mature nodes. Aprisa is the easiest digital implementation solution to adopt and the most efficient for both engineering and computing resources
Place-and-route for complex SoC designs
Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Its detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results (QoR) at a competitive runtime.
Reduced time-to-design closure
A unified data model brings real route information and parasitics to any engine and step in the flow. Designers can confidently know their design’s achievable PPA at pre-route stage, greatly reducing full-flow iterations
AI-driven macro placement technology
Expert designer quality macro placement at a fraction of the time and effort that it would take an experienced designer. Eliminates the need for full-flow iterations to lock down the optimal macro placement for a given design
Low power patented technology
Target low power as a primary design metric for power sensitive designs, without sacrificing performance. Designers choose the tradeoffs that meet their optimal PPA, reducing power cleanup on the last mile of the design tapeout